CircuitLM: A Multi-Agent LLM-Aided Design Framework for Generating Circuit Schematics from Natural Language Prompts

Published in 2026 IEEE International Conference on LLM-Aided Design (ICLAD), 2026

Citation (IEEE format): K. S. A. Hasan, S. R. Raiyan, H. M. Alvee and W. Sadik, "CircuitLM: A Multi-Agent LLM-Aided Design Framework for Generating Circuit Schematics from Natural Language Prompts," 2026 IEEE International Conference on LLM-Aided Design (ICLAD), 2026.

arXiv PDF Code/Data

@inproceedings{hasan2026circuitlm,
    title={{CircuitLM}: A Multi-Agent {LLM}-Aided Design Framework for Generating Circuit Schematics from Natural Language Prompts},
    author={Hasan, Khandakar Shakib Al and Raiyan, Syed Rifat and Alvee, Hasin Mahtab and Sadik, Wahid},
    booktitle={2026 IEEE International Conference on LLM-Aided Design (ICLAD)},
    year={2026},
    url={https://arxiv.org/abs/2601.04505}
}

Authors: Khandakar Shakib Al Hasan, Syed Rifat Raiyan, Hasin Mahtab Alvee, Wahid Sadik.
Abstract: Generating accurate circuit schematics from high-level natural language descriptions remains a persistent challenge in electronic design automation (EDA), as large language models (LLMs) frequently hallucinate components, violate strict physical constraints, and produce non-machine-readable outputs. To address this, we present CircuitLM, a multi-agent pipeline that translates user prompts into structured, visually interpretable $\texttt{CircuitJSON}$ schematics. The framework mitigates hallucination and ensures physical viability by grounding generation in a curated, embedding-powered component knowledge base through five sequential stages: (i) component identification, (ii) canonical pinout retrieval, (iii) chain-of-thought reasoning, (iv) JSON schematic synthesis, and (v) interactive force-directed visualization. We evaluate the system on a dataset of 100 unique circuit-design prompts using five state-of-the-art LLMs. To systematically assess performance, we deploy a rigorous dual-layered evaluation methodology: a deterministic Electrical Rule Checking (ERC) engine categorizes topological faults by strict severity (Critical, Major, Minor, Warning), while an LLM-as-a-judge meta-evaluator identifies complex, context-aware design flaws that bypass standard rule-based checkers. Ultimately, this work demonstrates how targeted retrieval combined with deterministic and semantic verification can bridge natural language to structurally viable, schematic-ready hardware and safe circuit prototyping. Our code and data are publicly available at this https URL.